SPI-4 is an interface for packet and cell transfer between a physical layer (PHY) device and a link layer device for aggregate bandwidths of OC-192 ATM, Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet applications. SPI-4 is a 16-bit interface based on low voltage differential signaling (LVDS) I/O, running at a minimum of 622 Mbits/sec. The SPI-4 interface provides in-band control and out-of-band status channel for flow control. The status channel is implemented as a 2-bit wide status bus that provides per-channel receiver status in a weighted round-robin fashion. The in-band control indicates channel address, start and end of packet, and checksum.
The data and status paths are accompanied by clock signals. Source synchronous clocking is used in which the data path is clocked on both rising and falling edges of the clock signal. The data path is based on a dual-data-rate scheme. SPI-4 includes training patterns that enable the design of dynamically aligned de-skew mechanisms.
SPI-4 supports simultaneous transfer of multiple protocols by using a simple control protocol to decouple interface operation from the actual data being transferred. SPI-4 uses in-band control words (payload, idle, and training control words) that are inserted between data transfer. Each SPI-4 data transfer is preceded by a payload control word that indicates the port address, a start-of-packet indicator, and an error control code based on DIP-4.
Computing DIP-4 parity bits requires circuitry that performs a series of XOR operations. Approaches used in the past for summing diagonally the words used in computing DIP-4 parity bits failed to meet the required performance target of SPI-4 of 105 MHz.
Thus what is needed is an efficient and cost effective method and apparatus for computing DIP-4 parity bits.